The continuing push to produce faster semiconductor devices with lower power consumption has resulted in the miniaturization of semiconductor devices. In particular, smaller gate oxide thickness and channel width are conducive to the low voltage and faster operation of transistor devices, such as complementary metal oxide (CMOS) transistors. With shrinking process geometries, comes a number of new design problems, however.
For instance, as gate dimensions are reduced, it has become necessary to adjust and better control the dimensions of the channel and doped regions of the substrate that are associated with the gate. This is necessary to prevent a number of short channel effects, such as hot carrier injection, leakage currents, drain induced barrier lowering (DIBL), threshold voltage variation and mobility degradation.
Consider, for instance, the dimensions of shallow junctions and pocket region structures. Shallow junctions, also referred to as source drain extensions, or light or middle-doped drain (LDD and MDD, respectively) regions, are implanted as extensions to the larger and more heavily doped source and drain regions, to reduce hot carrier injection-induced damage to gate dielectric layers and drifting threshold voltage. Hot carriers, electrons with higher than average energy, form because of the stronger electric fields produced in small transistor device geometries. Shallow junctions, implanted before sidewall formation and source and drain implantation, provide a doping gradient between the source and drain regions and the channel. The lowered electric field in the vicinity of the channel region of such devices reduces the formation of hot carriers.
Sub-0.1 micron transistor devices are also highly susceptible to leakage currents, or punch-through, when the transistor is off. Leakage currents can be reduced if the shallow junctions are formed with well-defined boundaries, as exemplified by an abrupt decrease in dopant concentration, to support low-voltage operation of the transistor and to define the width of the channel region of the transistor. The formation of abrupt shallow junctions can be problematic in certain instances, however.
For, instance, to establish p-type doped shallow junctions in a positive channel metal oxide semiconductor (PMOS) transistor, a typical p-type dopant is boron (B+). Small dopants, such as boron, are subject to undesirable enhanced diffusion into implantation-caused damage to the lattice structures of silicon substrates during thermal annealing. This phenomenon, known as transient enhanced diffusion (TED), is undesirable because it decreases the abruptness of the change in dopant concentrations from the shallow junction to a p-well or n-well that the shallow junction is formed in. TED deters the formation of shallow junctions having suitably shallow depths (e.g., less than about 40 nm). TED can also cause dopants, such as boron, to diffuse into the channel region, thereby causing an unfavorable change in the dopant concentration in the channel resulting in punch-through, an increase in electron trapping, a decrease in low-field hole mobility, and a degraded on-current drive.
Another approach to reduce leakage currents is to implant a lightly doped pocket or halo region, containing dopants of the opposite dopant type of the shallow junction, around the edges of the shallow junction. The dopants in the pocket region provide increases resistance in the channel region to reduce or prevent leakage currents. However, if the pocket regions on the source and drain sides of the transistor's channel region are too close to each other, then the pocket regions will overlap. Overlap, in turn, causes excessively high resistance in the channel region, thereby undesirably reducing the on-current of the device.
One approach to reduce excessively close shallow junctions or overlapping pockets regions, is to introduce off-set spacers on the sides of gates prior to dopant implantation. The off-set spacers act as mask during the implantation of dopants to prevent dopants of the source and drain shallow junctions or pocket regions from being too close to each after the transistor is thermally annealed. This approach is not entirely successful, however, because the extent of diffusion of p-type and n-type dopants during thermal annealing are substantially different than each other.
For instance, to establish n-type doped shallow junctions in a negative channel metal oxide semiconductor (NMOS) transistor, a typical n-type dopant is arsenic (As+) or phosphorus (P+) However, because of their higher mass and different electrical properties than boron, arsenic and phosphorus are not subject to TED to the same extent as boron. Consequently, the fabrication steps used to mitigate the short channel effects in PMOS transistors are not necessarily beneficial to mitigate the short channel effects in NMOS transistors. Indeed, if the junctions in an NMOS transistor are too far apart, this can detrimentally decrease the source to drain saturation current of the NMOS transistor, thereby reducing the operating speed of the device. Moreover, an abrupt shallow junction depth in NMOS transistors improves Vt roll-off, DIBL, gate-edge capacitance (Cge) and mobility degradation.
Heretofore, however, the fabrication processes for PMOS and NMOS transistors in CMOS devices have resulted in the formation of shallow junctions having substantially the same geometries. As such, the geometries of one or both of the NMOS and PMOS shallow junctions have not been simultaneously optimized in both transistor types. Because current CMOS devices are constructed with compromised NMOS and PMOS shallow junction geometries, the performance of these devices is also compromised.
Accordingly, what is needed in the art is an improved method of manufacturing shallow junctions having geometries that are separately optimized for NMOS and PMOS transistor configurations.